3-to-8 line decoder, demultiplexer with address latches inverting

文件：107.6 Kbytes 页数：19 Pages

PHI

PHI

3-to-8 line decoder, demultiplexer with address latches; inverting

1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to

文件：273.83 Kbytes 页数：16 Pages

NEXPERIA

安世

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件：65.099 Kbytes 页数：10 Pages

TI

德州仪器

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：381.06 Kbytes 页数：16 Pages

TI

德州仪器