74HC-HCT393中文资料SYC数据手册PDF规格书

General description

The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with

Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard

no. 7A.

The 74HC393; 74HCT393 contains 4-bit binary ripple counters with separate clocks

(1CP and 2 CP) and master reset (1MR and 2MR) inputs to each counter.

The operation of each half of the 74HC393; 74HCT393 is the same as the 74HC93;

74HCT93, except no external clock connections are required.

The counters are triggered by a HIGH-to-LOW transition of the clock inputs.

The counter outputs are internally connected to provide clock inputs to succeeding

stages. The outputs of the ripple counter do not change synchronously and should not be

used for high-speed address decoding.

The master resets (1MR and 2MR) are active-HIGH asynchronous inputs to each 4-bit

counter. A HIGH level on the nMR input overrides the clock and sets the outputs LOW.