LVCMOS Zero Delay Buffer

Not recommended for new designs. Please use 74FCT388915T instead. 0.5 MICRON CMOS Technology\nInput frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH)\nMax. output frequency: 133MHz\nPin and function compatible with MC88915\nFive non-inverting outputs, one inverting output, one 2x output, one ÷2 output\nall outputs are TTL-compatible\nOutput Skew < 500ps (ma;

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LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

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IDT

TSSOP16

ON

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SOP14

恩XP

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SOP-14

FAIRCHILD

仙童半导体

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