3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

文件：1.14603 Mbytes 页数：10 Pages

IDT

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

文件：1.14603 Mbytes 页数：10 Pages

IDT

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)

DESCRIPTION: The IDT54/74FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH) • Max. output frequency: 150MHz • Pin and

文件：145.69 Kbytes 页数：11 Pages

IDT

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)

DESCRIPTION: The IDT54/74FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH) • Max. output frequency: 150MHz • Pin and

文件：145.69 Kbytes 页数：11 Pages

IDT

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)

DESCRIPTION: The IDT54/74FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH) • Max. output frequency: 150MHz • Pin and

文件：145.69 Kbytes 页数：11 Pages

IDT