74F765-1中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74F764-1/765-1 DRAM Dual-ported Controller is a high-speed synchronous dual-port arbiter and timing generator that allows two microprocessors, microcontrollers, or any other memory accessing device to share the same block of DRAM. The device performs arbitration, signal timing, address multiplexing, and refresh address generation, replacing up to 25 discrete devices.

FEATURES

• Allows two microprocessors to access the same bank of dynamic RAM

• Performs arbitration, signal timing, address multiplexing and refresh

• 9 Address output pins allow direct control of up to 256K dynamic RAMs

• External address multiplexing enables control of 1Mbit (or greater) dynamic RAMs

• Separate refresh clock allows adjustable refresh timing

• 74F764-1 has an on-chip 18-bit address input latch

• 74F764-1/765-1 allow control of dynamic RAMs with row access times down to 40ns

• 74F764-1/765-1 output drivers designed for first reflected wave switching