74F647中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74F647 and 74F649 Transceivers/Registers consist of bus transceiver circuits with open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a High logic level. Output Enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or both.

FEATURES

• High impedance NPN base inputs for reduced loading (20µA in High and Low states)

• Independent registers for A and B buses

• Multiplexed real-time and stored data

• Choice of non-inverting and inverting data paths

• Open Collector outputs

• 300 mil wide 24-pin Slim Dip package