74F646数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

General Description
These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control G and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control G is Active LOW. In the isolation mode (control G HIGH), A data may be stored in the B register and/or B data may be stored in the A register.

特性 Features

■ Independent registers for A and B buses
■ Multiplexed real-time and stored data
■ 74F648 has inverting data paths
■ 74F646/74F646B have non-inverting data paths
■ 74F646B is a faster version of the 74F646
■ 3-STATE outputs
■ 300 mil slim DIP

简介

74F646属于集成电路（IC）的缓冲器驱动器接收器收发器。由制造生产的74F646缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。