Quad 2-Input OR Gate

General Description This device contains four independent gates, each of which performs the logic OR function.

文件：77.9 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Quad 2-input OR gate

FEATURE • Industrial temperature range available (–40°C to +85°C)

文件：69.06 Kbytes 页数：8 Pages

PHI

PHI

Quad 2-input OR gate

FEATURE • Industrial temperature range available (–40°C to +85°C) TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F32 4.1ns 8.2mA

文件：197.25 Kbytes 页数：9 Pages

NEXPERIA

安世

Quad 2-Input OR Gate

文件：128.66 Kbytes 页数：6 Pages

NSC

国半

Quad 2-input OR gate

恩XP

Quad 2-Input OR Gate

ONSEMI

安森美半导体

8-bit serial/parallel register with sign extend 3-State

DESCRIPTION The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the c

文件：80.62 Kbytes 页数：9 Pages

PHI

PHI

Octal Serial/Parallel Register with Sign Extend

General Description The ’F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATEÉ parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the r

文件：178.28 Kbytes 页数：10 Pages

NSC

国半

Octal Serial/Parallel Register with Sign Extend

General Description The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-STATE parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the ris

文件：53.91 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Octal Serial/Parallel Register with Sign Extend

General Description The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-STATE parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the ris

文件：53.91 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体