74AXP1G32GS中文资料Low-power 2-input OR gate数据手册Nexperia规格书

描述 Description

The 74AXP1G32 is a single 2-input OR gate.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

特性 Features

• Wide supply voltage range from 0.7 V to 2.75 V
• Low input capacitance; CI = 0.5 pF (typical)
• Low output capacitance; CO = 1.0 pF (typical)
• Low dynamic power consumption; CPD = 2.4 pF at VCC = 1.2 V (typical)
• Low static power consumption; ICC = 0.6 μA (85 °C maximum)
• High noise immunity
• Complies with JEDEC standard:
• JESD8-12A.01 (1.1 V to 1.3 V)
• JESD8-11A.01 (1.4 V to 1.6 V)
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A.01 (2.3 V to 2.7 V)

• ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
• CDM JESD22-C101E exceeds 1000 V

• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 2.75 V
• Low noise overshoot and undershoot < 10% of VCC
• IOFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from ‑40 °C to +85 °C