74AUP2G79GM中文资料74AUP2G79GM - Low-power dual D-type flip-flop; positive-edge trigger 数据手册Nexperia规格书

描述 Description

Low-power dual D-type flip-flop; positive-edge trigger - The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

特性 Features

·Wide supply voltage range from 0.8 V to 3.6 V
·High noise immunity
·Complies with JEDEC standards: ·JESD8-12 (0.8 V to 1.3 V)
·JESD8-11 (0.9 V to 1.65 V)
·JESD8-7 (1.2 V to 1.95 V)
·JESD8-5 (1.8 V to 2.7 V)
·JESD8-B (2.7 V to 3.6 V)