1. General description

The 74AUP2G32 is a dual 2-input OR gate. Schmitt-trigger action at all inputs makes the circuit

tolerant of slower input rise and fall times. This device ensures very low static and dynamic power

consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for

partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the

potentially damaging backflow current through the device when it is powered down.

2. Features and benefits

• Wide supply voltage range from 0.8 V to 3.6 V

• CMOS low power dissipation

• High noise immunity

• Low static power consumption; ICC = 0.9 μA (maximum)

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Overvoltage tolerant inputs to 3.6 V

• Low noise overshoot and undershoot < 10 of VCC

• IOFF circuitry provides partial Power-down mode operation

• Complies with JEDEC standards:

• JESD8-12 (0.8 V to 1.3 V)

• JESD8-11 (0.9 V to 1.65 V)

• JESD8-7 (1.2 V to 1.95 V)

• JESD8-5 (1.8 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• ESD protection:

• HBM JESD22-A114F Class 3A exceeds 5000 V

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101E exceeds 1000 V

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP2G32DC属于集成电路（IC） > 门和反相器。安世半导体(中国)有限公司制造生产的74AUP2G32DC门和反相器逻辑栅极和逆变器系列中的产品对单个逻辑信号执行基本逻辑运算（例如 AND、NOT、OR 等）。与触发器不同，它们不能够存储信息，不会对提供给其输入的信号立即做出响应。虽然早就被集成电路实施形式所取代，以用于实现复杂功能，但分立栅极仍可在仅需要非常简单逻辑功能的情况下使用。