74AUP1T1326GT中文资料74AUP1T1326GT - Low-power dual supply buffer/line driver; 3-state 数据手册Nexperia规格书

描述 Description

Low-power dual supply buffer/line driver; 3-state - The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry. The 74AUP1T1326 is designed for logic-level translation applications and combines the functions of the 74AUP1G32 and 74AUP1G126. The buffer/line driver is controlled by two output enable Schmitt trigger inputs (1OE and 2OE) through an OR-gate. The output enable inputs accept standard input signals and are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The output of the OR-gate is also available at output 1Y.

特性 Features

·Complies with JEDEC standard: JESD8-5 (1.8 V to 2.7 V)
·Complies with JEDEC standard: JESD8-7 (1.2 V to 1.95 V)
·Complies with JEDEC standard: JESD8-B (2.7 V to 3.6 V)
·ESD protection: CDM JESD22-C101C exceeds 1000 V
·ESD protection: HBM JESD22-A114E Class 2A exceeds 2000 V
·ESD protection: MM JESD22-A115-A exceeds 200 V
·High noise immunity
·IOFF circuitry provides partial Power-down mode operation
·Inputs accept voltages up to 3.6 V
·Latch-up performance exceeds 100 mA per JESD 78 Class II
·Low noise overshoot and undershoot < 10 % of VCC
·Low static power consumption; ICC = 0.9 μA (maximu)
·Multiple package options
·Specified from 40 °C to +85 °C
·Wide supply voltage range: VCC(A): 1.1 V to 3.6 V
·Wide supply voltage range: VCC(B): 1.1 V to 3.6 V

应用 Application

显示更多参数类型型号Product statusVCC (V)Logic switching levelsOutput drive capability (mA)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name74AUP1T1326GTProduction1.1 - 3.6CMOS+/- 1.9701ultra low-40~1253276.1157XSON8Package型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）74AUP1T1326GTXSON8(SOT833-1)SOT833-1Reel 7\" Q1/T1Activep3174AUP1T1326GT,115(9352 860 82115)品质、可靠性及化学成分型号可订购的器件编号化学成分RoHS / RHF无铅转换日期MSLMSL无铅74AUP1T1326GT74AUP1T1326GT,11574AUP1T1326GTAlways Pb-free11品质及可靠性免责声明文档 (6)文件名称标题类型日期74AUP1T1326Low-power dual supply buffer/line driver; 3-stateData sheet2017-10-17AN10161PicoGate Logic footprintsApplication note2002-10-29AN10156Sorting through the low voltage logic mazeApplication note2013-03-1375017285Logic selection guide 2016Selection guide2015-01-07SOT833-1_115Standard product orientation 12NC ending 115Packing2013-04-05SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyOutline drawing2018-06-04支持在此页面中寻找您的设计问题答案。如有提供，您可以在我们的Nexperia支持社区找到相关信息，或者您可以找到Nexperia模型和设计工具。订购Powered by 经销商在线购买Arrow Electronics在线购买Avnet Express在线购买Chip One Stop在线购买DigiKey在线购买Farnell Europe在线购买Future Electronics在线购买Mouser Electronics在线购买Newark在线购买Newark element14在线购买Rochester Electronics在线购买样品Nexperia客户可通过我们的销售机构或直接通过在线样品商店订购样品。 https://extranet.nexperia.com.样品订单通常需要2-4天寄送时间。如果您尚未取得Nexperia的直接采购帐号，我们的全球与区域经销网络可以协助您取得样品。工作机会
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