74AUP1G07数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G07 is a single buffer gate with an open drain output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.

特性 Features

•Advanced Ultra Low Power (AUP) CMOS
•Supply Voltage Range from 0.8V to 3.6V
•4mA Output Drive at 3.0V
•Low Static power consumption

应用 Application

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\t\tSuited for battery and low power needs
\t•
\t\tWide array of products such as:
\t•
\t\tTablets, E-readers