74AUP1G07中文资料Single-gate数据手册Diodes规格书

描述 Description

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G07 is a single buffer gate with an open drain output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.

特性 Features

•Advanced Ultra Low Power (AUP) CMOS
•Supply Voltage Range from 0.8V to 3.6V
•4mA Output Drive at 3.0V
•Low Static power consumption

应用 Application

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\t\tSuited for battery and low power needs
\t•
\t\tWide array of products such as:
\t•
\t\tTablets, E-readers

简介

74AUP1G07属于集成电路（IC）的缓冲器驱动器接收器收发器。由制造生产的74AUP1G07缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。