74ALVCHR16601DLG4中文资料德州仪器数据手册PDF规格书

FEATURES

· Member of the Texas Instruments Widebus™

Family

· UBT™ Transceiver Combines D-Type Latches

and D-Type Flip-Flops for Operation in

Transparent, Latched, or Clocked Modes

· Operates From 1.65 V to 3.6 V

· Max tpd of 4.4 ns at 3.3 V

· ±12-mA Output Drive at 3.3 V

· Outputs Ports Have Equivalent 26-W Series

Resistors, So No External Resistors Are

Required

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

- 2000-V Human-Body Model (A114-A)

- 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 18-bit universal bus transceiver is designed for

1.65-V to 3.6-V VCC operation.

The SN74ALVCHR16601 combines D-type latches

and D-type flip-flops to allow data flow in transparent,

latched, clocked, and clock-enabled modes.

Data flow in each direction is controlled by

output-enable (OEAB and OEBA), latch-enable

(LEAB and LEBA), and clock (CLKAB and CLKBA)

inputs. The clock can be controlled by the

clock-enable (CLKENAB and CLKENBA) inputs. For

A-to-B data flow, the device operates in the

transparent mode when LEAB is high. When LEAB is

low, the A data is latched if CLKAB is held at a high

or low logic level. If LEAB is low, the A data is stored

in the latch/flip-flop on the low-to-high transition of

CLKAB. When OEAB is low, the outputs are active.

When OEAB is high, the outputs are in the

high-impedance state.