74ALVCH16952中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bi-directional busses. Data applied to the inputs is entered and stored on the rising edge of the clock (CPXX, where X is AB or BA) provided that the clock enable (CEXX) is LOW. The data is then present at the 3-State output buffers, but is only accessible when the output enable input (OEXX) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.

FEATURES

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTETM flow-through pin-out architecture

• Low inductance, multiple center power and ground pins for

minimum noise and ground bounce

• Direct interface with TTL levels

• Output drive capability 50Ω transmission lines @ 85°C