1 General description

The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with 3-state outputs for bus

oriented applications.

The 74ALVCH16827 consists of two 10-bit sections with separate output enable signals.

For either 10-bit buffer section, the two output enable (1OE0 and 1OE1 or 2OE0 and

2OE1) inputs must both be active. If either output enable input is high, the outputs of that

10-bit buffer section are in high impedance state.

The 74ALVCH16827 has active bus hold circuitry which is provided to hold unused or

floating data inputs at a valid logic level. This feature eliminates the need for external

pull-up or pull-down resistors.

2 Features and benefits

• Wide supply voltage range of 1.2V to 3.6V

• CMOS low power consumption

• MultiByte flow-through standard pin-out architecture

• Low inductance multiple VCC and GND pins for minimum noise and ground bounce

• Direct interface with TTL levels (2.7 V to 3.6 V)

• Bus hold on data inputs

• Output drive capability 50 Ω transmission lines at 85 °C

• Current drive ±24 mA at 3.0 V

• Complies with JEDEC standards:

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V)

• ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

– CDM JESD22-C101E exceeds 1000 V

74ALVCH16827属于集成电路（IC） > 缓冲器，驱动器，接收器，收发器。安世半导体(中国)有限公司制造生产的74ALVCH16827缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。