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74ALVCH162601DGG集成电路(IC)通用总线功能规格书PDF中文资料
厂商型号 |
74ALVCH162601DGG |
参数属性 | 74ALVCH162601DGG 封装/外壳为56-TFSOP(0.240",6.10mm 宽);包装为卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带;类别为集成电路(IC) > 通用总线功能;产品描述:IC UNIV BUS TXRX 18BIT 56TSSOP |
功能描述 | 18-bit universal bus transceiver with 30 Ω termination resistor; 3-state |
文件大小 |
233.64 Kbytes |
页面数量 |
15 页 |
生产厂商 | Nexperia B.V. All rights reserved |
企业简称 |
NEXPERIA【安世】 |
中文名称 | 安世半导体(中国)有限公司官网 |
原厂标识 | |
数据手册 | |
更新时间 | 2024-6-14 10:00:00 |
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74ALVCH162601DGG规格书详情
1. General description
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is controlled by
output enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CPAB and CPBA)
inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is
LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When
OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
To ensure the high impedance state during power up or power down, OEBA and OEAB should
be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or LOW output stage.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
2. Features and benefits
• CMOS low power consumption
• MultiByte flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Direct interface with TTL levels
• Bus hold on data inputs
• Integrated 30 Ω termination resistors.
• Complies with JEDEC standards:
• JESD8-5 (2.3 V to 2.7 V)
• JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
• CDM JESD22-C101E exceeds 1000 V
74ALVCH162601DGG属于集成电路(IC) > 通用总线功能。安世半导体(中国)有限公司制造生产的74ALVCH162601DGG通用总线功能通用总线功能系列产品是元件级产品,用于处理或操作一系列(通常为 8 个或更多)并行逻辑信号(称为总线)。所执行的功能包括临时存储要发送或接收的数据,执行缓冲以允许输出电流容量有限的器件(例如微处理器)通过远距离互连高速传输数据,以及调换或移动总线内的位顺序等。
产品属性
- 产品编号:
74ALVCH162601DGG,1
- 制造商:
Nexperia USA Inc.
- 类别:
集成电路(IC) > 通用总线功能
- 系列:
74ALVCH
- 包装:
卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带
- 逻辑类型:
通用总线收发器
- 电路数:
18 位
- 电流 - 输出高、低:
12mA,12mA
- 电压 - 供电:
1.2V ~ 3.6V
- 工作温度:
-40°C ~ 85°C
- 安装类型:
表面贴装型
- 封装/外壳:
56-TFSOP(0.240",6.10mm 宽)
- 供应商器件封装:
56-TSSOP
- 描述:
IC UNIV BUS TXRX 18BIT 56TSSOP
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
NXP/恩智浦 |
22+ |
TSSOP-14 |
8880 |
原装认准芯泽盛世! |
询价 | ||
Nexperia |
23/22+ |
NA |
9000 |
代理渠道.实单必成 |
询价 | ||
NXP/恩智浦 |
23+ |
TSSOP-14 |
30000 |
原装正品公司现货,假一赔十! |
询价 | ||
NXP/恩智浦 |
21+ |
TSSOP-14 |
8800 |
公司只做原装正品 |
询价 | ||
NXP/恩智浦 |
22+ |
TSSOP-14 |
6000 |
询价 | |||
Nexperia(安世) |
22+ |
TSSOP-56 |
9852 |
只做原装正品现货,或订货假一赔十! |
询价 | ||
NXP |
21+ |
TSSOP |
1106 |
原装现货假一赔十 |
询价 | ||
Nexperia USA Inc. |
21+ |
56-TFSOP(0.240,6.10mm 宽) |
12000 |
正规渠道/品质保证/原装正品现货 |
询价 | ||
NXP/恩智浦 |
21+ |
TSSOP-14 |
8080 |
只做原装,质量保证 |
询价 | ||
23+ |
N/A |
88000 |
一级代理放心采购 |
询价 |