74ALVC16827MTD集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

General Description

The ALVC16827 contains twenty non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver carrying parity. The device is byte controlled. Each byte has NOR output enables for maximum control flexibility.

The 74ALVC16827 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74ALVC16827 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain ing low CMOS power dissipation.

Features

■ 1.65V to 3.6V VCC supply operation

■ 3.6V tolerant inputs and outputs

■ tPD

3.0 ns max for 3.0V to 3.6V VCC

3.5 ns max for 2.3V to 2.7V VCC

6.0 ns max for 1.65V to 1.95V VCC

■ Power-off high impedance inputs and outputs

■ Supports live insertion and withdrawal (Note 1)

■ Uses patented noise/EMI reduction circuitry

■ Latchup conforms to JEDEC JED78

■ ESD performance:

Human body model > 2000V

Machine model > 200V