Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26??Series Resistors in Outputs

General Description The ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. The ALVC162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications suc

文件：89.92 Kbytes 页数：7 Pages

Fairchild

仙童半导体

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs

General Description\nThe ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. The ALVC162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications such ■ Compatible with PC100 DIMM module specifications\n■ 1.65V to 3.6V VCC specifications provided\n■ 3.6V tolerant inputs and outputs\n■ 26Ω series resistors in outputs\n■ tPD (CLK to On)\n   5.4 ns max for 3.0V to 3.6V VCC\n   6.3 ns max for 2.3V to 2.7V VCC\n   9.2 ns max for 1.65V to 1.95V VCC\n■ P;

ONSEMI

安森美半导体

18-bit Universal Bus Driver with 3-state Outputs

Description The HD74ALVC162835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode when the latch enable (LE) is high. When LE is low, the A data is latched if the c

文件：241.7 Kbytes 页数：16 Pages

RENESAS

瑞萨

18-bit Universal Bus Driver with 3-state Outputs

Description The HD74ALVC162835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Features • Meets “PC SDRAM registered DIMM design support document, Rev. 1.2” • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce

文件：65.16 Kbytes 页数：15 Pages

HitachiHitachi Semiconductor

日立日立公司

18-bit Universal Bus Driver with 3-state Outputs

Description The HD74ALVC162835A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode when the latch enable (LE) is high. When LE is low, the A data is latched if the

文件：62.49 Kbytes 页数：16 Pages

HitachiHitachi Semiconductor

日立日立公司