74ALVC125PW集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

DESCRIPTION

The 74ALVC125 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times.

FEATURES

• Wide supply voltage range from 1.65 to 3.6 V

• Complies with JEDEC standard:

JESD8-7 (1.65 to 1.95 V)

JESD8-5 (2.3 to 2.7 V)

JESD8B/JESD36 (2.7 to 3.6 V)

• 3.6 V tolerant inputs/outputs

• CMOS low power consumption

• Direct interface with TTL levels (2.7 to 3.6 V)

• Power-down mode

• Latch-up performance exceeds 250 mA

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.