74ALS652-1D中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74LAS651 and 74ALS652 transceivers/registers consist of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes High. Output enable (OEAB, OEBA) and select (SAB, SBA) pins are provided for bus management. The 74LAS651-1 and 74ALS652-1 will sink 48mA if the VCC is limited to 5.0V ± 0.25V.

FEATURES

• Independent registers for A and B buses

• Multiplexed real-time and stored data

• Choice of non-inverting and inverting data paths

• 3-State outputs

• The -1 versions sinks 48mA IOL within the ±5 VCC range