1. General description

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with

Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data

inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary

outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the clock

input. Information on the data input is transferred to the Q output on the LOW to HIGH transition

of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock

transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall

times.

2. Features and benefits

• Balanced propagation delays

• All inputs have Schmitt-trigger actions

• Inputs accept voltages higher than VCC

• Input levels:

• For 74AHC74: CMOS level

• For 74AHCT74: TTL level

• ESD protection:

• HBM EIA/JESD22-A114E exceeds 2000 V

• MM EIA/JESD22-A115-A exceeds 200 V

• CDM EIA/JESD22-C101C exceeds 1000 V

• Multiple package options

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74AHCT74属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的74AHCT74触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。