74AHCT595PW-Q100中文资料8-bit serial-in/serial-out or parallel-out shift register with output latches数据手册Nexperia规格书

描述 Description

The 74AHC595-Q100; 74AHCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.
The 74AHC595-Q100; 74AHCT595-Q100 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Balanced propagation delays
• All inputs have Schmitt trigger action
• Inputs accept voltages higher than VCC
• Input levels:
• The 74AHC595-Q100 operates with CMOS input levels
• The 74AHCT595-Q100 operates with TTL input levels

• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)

• Multiple package options

应用 Application

• Serial-to-parallel data conversion
• Remote control holding register