74AHC273PW-Q100中文资料Octal D-type flip-flop with reset; positive-edge trigger数据手册Nexperia规格书

描述 Description

The 74AHC273-Q100; 74AHCT273-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC273-Q100; 74AHCT273-Q100 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
All outputs are forced LOW, independent of clock or data inputs, by a LOW on the MR input.
The device is useful for applications where only the true output is required and the clock and master reset are common to all storage elements.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than VCC
• Ideal buffer for MOS microcontroller or memory
• Common clock and master reset
• Input levels:
• For 74AHC273-Q100: CMOS level
• For 74AHCT273-Q100: TTL level

• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

• Multiple package options