74AHC157PW-Q100中文资料Quad 2-input multiplexer数据手册Nexperia规格书

描述 Description

The 74AHC157-Q100; 74AHCT157-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.
The 74AHC157-Q100; 74AHCT157-Q100 is a quad 2-input multiplexer which selects 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74AHC157-Q100; 74AHCT157-Q100. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The 74AHC157-Q100; 74AHCT157-Q100 is logic implementation of a 4-pole, 2-position switch. The logic levels applied to S, determines the position of the switch.
The logic equations are:
1Y = E (1I1 x S + 1I0 x S)
2Y = E (2I1 x S + 2I0 x S)
3Y = E (3I1 x S + 3I0 x S)
4Y = E (4I1 x S + 4I0 x S)
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40°C to +85°C and from -40°C to +125°C

• Balanced propagation delays
• All inputs have a Schmitt-trigger action
• Inputs accept voltages higher than VCC
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Input levels:
• For 74AHC157-Q100: CMOS level
• For 74AHCT157-Q100: TTL level

• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

• Multiple package options