74AHC138中文资料standard-logic数据手册Diodes规格书

描述 Description

The 74AHC138 is is an advanced high speed CMOS device.
The device accepts a three bit binary weighted address on
input pins A0, A1 and A2 and when enab°C will porduce
one active low output with the remaing seven being high.
There are two active LOW enable inputs 1 and 2, and one
active HIGH enable input E3. The disab°C device state
results in all outputs being high. The enable state occurs with
1 and 2 asserted low and E3 asserted high.
The multiple enable lines allow for the parallel expansion of
decoders to create 4-to-16 line versions with no additional
parts and 5-to-32 versions with the addition of a single
inverter.

应用 Application

Memory chip select decodingDemultiplexingSingle line peripheral controlAllow simple serial bit streams from a microcontroller
to control as many peripheral lines as needed.
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