74ACT16657DLR集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

74ACT16657DLR属于集成电路（IC）的缓冲器驱动器接收器收发器。由美国德州仪器公司制造生产的74ACT16657DLR缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。

Members of the Texas Instruments

WidebusE Family

Inputs Are TTL-Voltage Compatible

Flow-Through Architecture Optimizes

PCB Layout

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

EPICE (Enhanced-Performance Implanted

CMOS) 1-mm Process

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) Packages Using

25-mil Center-to-Center Pin Spacings and

380-mil Fine-Pitch Ceramic Flat (WD)

Packages Using 25-mil Center-to-Center

Pin Spacings

description

The ’ACT16657 contain two noninverting octal

transceiver sections with separate parity

generator/checker circuits and control signals.

For either section, the transmit/receive (1T/R or

2T/R) input determines the direction of data flow.

When 1T/R (or 2T/R) is high, data flows from the

1A (or 2A) port to the 1B (or 2B) port (transmit

mode); when 1T/R (or 2T/R) is low, data flows

from the 1B (or 2B) port to the 1A (or 2A) port

(receive mode). When the output-enable (1OE or

2OE) input is high, both the 1A (or 2A) and 1B (or

2B) ports are in the high-impedance state.

Odd or even parity is selected by a logic high or

low level, respectively, on the 1ODD/EVEN (or

2ODD/EVEN) input. 1PARITY (or 2PARITY)

carries the parity bit value; it is an output from the

parity generator/checker in the transmit mode and

an input to the parity generator/checker in the

receive mode.

In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or

2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or

2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on

the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus

bits plus parity bit) are high.