74ACT16651中文资料具有三态输出的 16 位收发器和寄存器数据手册TI规格书

描述 Description

The SN54ACT16651 and 74ACT16651 are 16-bit bus transceivers that consist of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. These devices can be used as two 8-bit transceivers or one 16-bit transceiver.
Complementary output-enable (OEAB and ) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN54ACT16651 and 74ACT16651.
 
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and . In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
The 74ACT16651 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ACT16651 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16651 is characterized for operation from -40°C to 85°C.
 
 
 

特性 Features

• Members of the Texas Instruments WidebusTM Family
• Inputs Are TTL-Voltage Compatible
• Inverting Data Paths
• Independent Registers and Enables for A and B Buses
• Multiplexed Real-Time and Stored Data
• Flow-Through Architecture Optimizes PCB Layout
• Distributed VCC and GND Pin Configurations MinimizeHigh-Speed Switching Noise
• EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Packaged in Plastic 300-mil Shrink Small-Outline (DL) Packagesand 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-milCenter-to-Center Pin Spacings  EPIC and Widebus are trademarks of Texas Instruments Incorporated.