74ACT11244DWR.A中文资料德州仪器数据手册PDF规格书

3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

Inputs Are TTL-Voltage Compatible

Flow-Through Architecture Optimizes

PCB Layout

Center-Pin VCC and GND Configurations to

Minimize High-Speed Switching Noise

EPIC (Enhanced-Performance Implanted

CMOS) 1-m Process

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, and Standard Plastic 300-mil

DIPs (NT)

description

ThIs octal buffer or line driver is designed specifically to improve both the performance and density of 3-state

memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the

’ACT11240, this device provides the choice of various combinations of inverting and noninverting outputs.

The 74ACT11244 is characterized for operation from −40°C to 85°C.