74ACT11074DBR.A中文资料德州仪器数据手册PDF规格书

Inputs Are TTL-Voltage Compatible

Center-Pin VCC and GND Configurations to

Minimize High-Speed Switching Noise

EPIC (Enhanced-Performance Implanted

CMOS) 1-
m Process

500-mA Typical Latch-Up Immunity

at 125°C

Package Options Include Plastic

Small-Outline (D) and Shrink Small-Outline

(DB) Packages, and Standard Plastic

300-mil DIPs (N)

description

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)

or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR

are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs

on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly

related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed

without affecting the levels at the outputs.

The 74ACT11074 is characterized for operation from –40°C to 85°C.