20-bit bus interface latch 3-State

DESCRIPTION The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Live insertion/extraction permitted • Extra data width for wide address/data paths or buses carrying parity

文件：82.19 Kbytes 页数：10 Pages

PHI

PHI

20-bit bus interface latch 3-State

DESCRIPTION The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Live insertion/extraction permitted • Extra data width for wide address/data paths or buses carrying parity

文件：82.19 Kbytes 页数：10 Pages

PHI

PHI

20-bit bus interface latch 3-State

DESCRIPTION The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Live insertion/extraction permitted • Extra data width for wide address/data paths or buses carrying parity

文件：82.19 Kbytes 页数：10 Pages

PHI

PHI

TSSOP-24

TI

德州仪器

上传：深圳市安富世纪电子有限公司

DIP-14

FSL

佛山照明

上传：深圳市鸿昌盛电子科技有限公司