10-bit bus interface latch 3-State

DESCRIPTION The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, lig

文件：69.84 Kbytes 页数：6 Pages

PHI

PHI

10-bit bus interface latch; 3-state

General description The 74ABT841 high performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT841 bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. Fe

文件：304.74 Kbytes 页数：15 Pages

恩XP

10-bit bus interface latch 3-State

DESCRIPTION The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, lig

文件：69.84 Kbytes 页数：6 Pages

PHI

PHI

10-bit bus interface latch; 3-state

General description The 74ABT841 high performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT841 bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. Fe

文件：304.74 Kbytes 页数：15 Pages

恩XP

10-bit bus interface latch 3-State

DESCRIPTION The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, lig

文件：69.84 Kbytes 页数：6 Pages

PHI

PHI

10-bit bus interface latch; 3-state

General description The 74ABT841 high performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT841 bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. Fe

文件：304.74 Kbytes 页数：15 Pages

恩XP

10-bit bus interface latch 3-State

DESCRIPTION The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, lig

文件：69.84 Kbytes 页数：6 Pages

PHI

PHI

10-bit bus interface latch; 3-state

General description The 74ABT841 high performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT841 bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. Fe

文件：304.74 Kbytes 页数：15 Pages

恩XP

10-bit bus interface latch 3-State

DESCRIPTION The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, lig

文件：69.84 Kbytes 页数：6 Pages

PHI

PHI

10-bit bus interface latch 3-State

DESCRIPTION The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, lig

文件：69.84 Kbytes 页数：6 Pages

PHI

PHI