Octal D-Type Flip-Flop with Clock Enable

General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setu

文件：101.67 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20TSSOP

ONSEMI

安森美半导体

Octal D-Type Flip-Flop with Clock Enable

General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setu

文件：101.67 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Octal D-Type Flip-Flop with Clock Enable

General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setu

文件：101.67 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Octal D-type flip-flop with enable

DESCRIPTION The 74ABT377A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Ideal for addressable register applications • 8-bit positive edge-triggered register • Enable for address and data synchronization appli

文件：55.93 Kbytes 页数：12 Pages

PHI

PHI