Octal D-Type Flip-Flop

General Description The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one

文件：112.29 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Octal D-Type Flip-Flop

General Description The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one

文件：112.29 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Octal D-Type Flip-Flop

General Description The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one

文件：112.29 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Octal D-Type Flip-Flop

General Description The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one

文件：112.29 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Octal D-Type Flip-Flop

General Description The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one

文件：112.29 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Octal D-Type Flip-Flop

General Description The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one

文件：112.29 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Package：20-SSOP（0.209"，5.30mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20SSOP

ONSEMI

安森美半导体

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20TSSOP

ONSEMI

安森美半导体

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20TSSOP

ONSEMI

安森美半导体