18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：86.11 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：86.11 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：86.11 Kbytes 页数：12 Pages

PHI

PHI

18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：133.15 Kbytes 页数：9 Pages

TI

德州仪器

18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：235.37 Kbytes 页数：14 Pages

TI

德州仪器

18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：388.7 Kbytes 页数：17 Pages

TI

德州仪器