74194中文资料意法半导体数据手册PDF规格书

DESCRIPTION

TheM54/74HC194 isahigh speed CMOS 4BIT PIPO SHIFT REGISTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This SHIFT REGISTER is designed to in corporate virtually allof thefeaturesasystem designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, clear line. The register has four distinct modes of operation : PARALLEL (broadside) LOAD ; SHIFT RIGHT (in the direction QA QD); SHIFT LEFT ; INHIBIT CLOCK (do nothing). Synchronous parallel loading is accomplished byapplying thefour databitsand taking both mode control inputs, S0 and S1 high.

. HIGH SPEED

tPD = 12 ns (TYP.) AT VCC = 5 V

. LOW POWER DISSIPATION

ICC = 4 µA (MAX.) AT TA = 25 °C

. OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

. SYMMETRICAL OUTPUT IMPEDANCE

IOH = IOL = 4 mA (MIN.)

. BALANCED PROPAGATION DELAYS

tPLH = tPHL

. HIGH NOISE IMMUNITY

VNIH = VNIL = 28 VCC (MIN.)

. WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V

. PIN AND FUNCTION COMPATIBLE WITH 54/74LS194