4-bit D-type Register (with 3-state Outputs)

Description The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. The input disable allows the

文件：56.75 Kbytes 页数：9 Pages

HitachiHitachi Semiconductor

日立日立公司

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

文件：69.04 Kbytes 页数：10 Pages

PHI

飞利浦

4-bit D-type Register (with 3-state Outputs)

Description\nThe four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level.\nThe input disable allows the fl • High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF)\n• High Output Current: Fanout of 10 LSTTL Loads\n• Wide Operating Voltage: VCC = 2 to 6 V\n• Low Input Current: 1 µA max\n• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C);

HITACHI

日立

TRI-STATE Quad Registers

文件：131.38 Kbytes 页数：6 Pages

NSC

国半

TTL HD74/HD74S Series

文件：143.51 Kbytes 页数：4 Pages

HitachiHitachi Semiconductor

日立日立公司

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：562.82 Kbytes 页数：19 Pages

TI

德州仪器