72V36100L7-5PFG集成电路（IC）的FIFO存储器规格书PDF中文资料

DESCRIPTION:

The IDT72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits:

• Flexible x36/x18/x9 Bus-Matching on both read and write ports

• The period required by the retransmit operation is fixed and short.

• The first word data latency period, from the time the first word is

written to an empty FIFO to the time it can be read, is fixed and short.

• Asynchronous/Synchronous translation on the read or write ports

• High density offerings up to 4 Mbit

FEATURES:

• Choose among the following memory organizations:

IDT72V36100 - 65,536 x 36

IDT72V36110 - 131,072 x 36

• Higher density, 2Meg and 4Meg SuperSync II FIFOs

• Up to 166 MHz Operation of the Clocks

• User selectable Asynchronous read and/or write ports (PBGA Only)

• User selectable input and output port bus-sizing

- x36 in to x36 out

- x36 in to x18 out

- x36 in to x9 out

- x18 in to x36 out

- x9 in to x36 out

• Big-Endian/Little-Endian user selectable byte representation

• 5V input tolerant

• Fixed, low first word latency

• Zero latency retransmit

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

• Selectable synchronous/asynchronous timing modes for Almost

Empty and Almost-Full flags

• Program programmable flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• JTAG port, provided for Boundary Scan function (PBGA Only)

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic

Ball Grid Array (PBGA) (with additional features)

• Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/

72V3670/72V3680/72V3690) family

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information