7290820BCG中文资料瑞萨数据手册PDF规格书

• 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s

• Per-channel variable or constant throughput delay

• Automatic identification of ST-BUS®/GCI interfaces

• Accept streams of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s

• Automatic frame offset delay measurement

• Per-stream frame delay offset programming

• Per-channel high impedance output control

• Per-channel Processor Mode

• Control interface compatible to Intel/Motorola CPUs

• Connection memory block programming

• IEEE-1149.1 (JTAG) Test Port

• Available in 84-pin Plastic Leaded Chip Carrier (PLCC),

100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack