72261中文资料16K x 9 SuperSync FIFO, 5.0V数据手册Renesas规格书

描述 Description

The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)

特性 Features

Pin-compatible with the 722x1 SuperSync FIFOs
10ns read/write cycle time (8ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing simultaneously)
Available in 64-pin TQFP and STQFP packages
Industrial temperature range (–40C to +85C) is available