丝印：487G-25LF；Package：TSSOP；QUAD PLL FOR DTV

Features • Packaged in 16-pin TSSOP (Pb-free) • Replaces multiple crystals and oscillators • Input crystal or clock frequency of 27 MHz • Zero ppm frequency synthesis error • Duty cycle of 45/55 • Operating voltage of 3.3 V • Advanced, low power CMOS process

文件：354 Kbytes 页数：8 Pages

RENESAS

瑞萨

Quad PLL for DTV

文件：150.48 Kbytes 页数：6 Pages

ICST

Quad PLL for DTV

文件：150.48 Kbytes 页数：6 Pages

ICST

Quad PLL for DTV

文件：150.48 Kbytes 页数：6 Pages

ICST