3D3522H-1中文资料DATADELAY数据手册PDF规格书

FUNCTIONAL DESCRIPTION

The 3D3522 product family consists of monolithic CMOS Manchester Decoders. The unit accepts at the RX input a bi-phase-level, embedded-clock signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. The recovered clock and data signals are presented on CLK and DATB, respectively, with the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input baud rate may vary by as much as ±15 from the nominal device baud rate without compromising the integrity of the information received.

FEATURES

• All-silicon, low-power CMOS technology

• 3.3V operation

• CMOS compatible inputs and outputs

• Vapor phase, IR and wave solderable

• Auto-insertable (DIP pkg.)

• Low ground bounce noise

• Maximum data rate: 50 MBaud

• Data rate range: ±15