26LS32D中文资料QUAD EIA–422/3 Line Receiver with Three–State Outputs数据手册恩XP规格书

描述 Description

Motorola′s Quad EIA–422/3 Receiver features four independent receiver chains which comply with EIA Standards for the Electrical Characteristics of Balanced/Unbalanced Voltage Digital Interface Circuits.
Receiver outputs are 74LS compatible, three–state structures which are forced to a high impedance state when Pin 4 is a Logic “0” and Pin 12 is a Logic “1.”
• Four Independent Receiver Chains
• Three–State Outputs
• High Impedance Output Control Inputs
   (PIA Compatible)
• Internal Hysteresis – 30 mV (Typical) @ Zero Volts Common Mode
• Fast Propagation Times – 25 ns (Typical)
• TTL Compatible
• Single 5.0 V Supply Voltage
• Fail–Safe Input–Output Relationship. Output Always High When Inputs
   Are Open, Terminated or Shorted
• 6.0 k Minimum Input Impedance