23S08T-4DCG中文资料瑞萨数据手册PDF规格书

FEATURES:

• Phase-Lock Loop Clock Distribution for Applications ranging

from 10MHz to 133MHz operating frequency

• Distributes one clock input to two banks of four outputs

• Separate output enable for each output bank

• External feedback (FBK) pin is used to synchronize the outputs

to the clock input

• Output Skew <200 ps

• Low jitter <200 ps cycle-to-cycle

• 1/2x, 1x, 2x, 4x output options (see table):

– IDT23S08T-1 1x

– IDT23S08T-2 1x, 2x

– IDT23S08T-3 2x, 4x

– IDT23S08T-4 2x

– IDT23S08T-5 1/2x

• No external RC network required

• Operates at 2.5V VDD

• Spread spectrum compatible

• Available in SOIC package