3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five outputs • Zero Input-Output Delay • Output Skew

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3.3V Zero Delay Clock Buffer

The 2305A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305A is an 8-pin version of Phase-Lock Loop Clock Distribution\n10MHz to 133MHz operating frequency\nDistributes one clock input to one bank of five outputs\nZero Input-Output Delay\nOutput Skew < 250ps\nLow jitter <200 ps cycle-to-cycle\nIDT2305A-1 for Standard Drive\nIDT2305A-1H for High Drive\nNo external RC network require;

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Package：8-SOIC（0.154"，3.90mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLK BUFFER ZD 3.3V 8-SOIC

Renesas Electronics America Inc

Package：8-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLK BUFFER ZD 3.3V 8-SOIC

Renesas Electronics America Inc

Package：8-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLK BUFFER ZD 3.3V 8-SOIC

Renesas Electronics America Inc