21A40-03中文资料ETC数据手册PDF规格书

Description

The 21140 interfaces with the PCI bus using onchip control and status

registers (CSRs), and a shared CPU memory area that is set up mainly during

initialization、This minimizes the processor involvement in the 21140 operation

during normal reception and transmission、The 21140 is compliant with the

PCT Local Brs Specifeation, Revision 2.0,Bus traffic is also minimized by

ltering out received runt frames and by automatically retransmitting collided

frames without needing to repeat a fetch from shared memory:

On the network side, tbe 21140 provides two ports: a serial (SRL) 10-Mbys

Port and a media independent interface/symbol (MISYMD) 100-Mbys port.

The 10-Mbys port provides a direct interface to the external 10-Mb/s ffont-end

decoder (BNDEC), The 100-Mbys port supports two operational modes: a direct

interface to the external 100-Mb/s RNDEC and a full implementation of the

MIT standard. The 21140 includes the onchip physical coding sublayer (PC8)

and the scrambler for efficient 100BASE-T (CAT5 cable) implementation,It is

also capable of functioning in a full-duplex environment for both the 10-Mbys

and 100-Mb/s ports,