丝印：211；Package：4BallWLCSP；250mA Single LDO with Low IQ, Low Noise and High PSRR LDO

250mA Single LDO with Low IQ, Low Noise and High PSRR LDO The ISL9021 is a single LDO providing high performance low input voltage, high PSRR. It delivers guaranteed continuous 250mA load current and is stable with 1µF to 4.7µF of output capacitance (±30) with an ESR range of 5mΩ to 400mΩ. Featu

文件：494.85 Kbytes 页数：10 Pages

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丝印：211；Package：SOT26(TSOP-6)；N-Channel Enhancement Mode Power MOSFET

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LRC

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丝印：211；Package：SOT26(TSOP-6)；N-Channel Enhancement Mode Power MOSFET

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LRC

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丝印：211；Package：TO-94；Two-Phase DC Fan Driver with FG

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SDC

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丝印：211；Package：TO-94；Two-Phase DC Fan Driver with FG

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SDC

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丝印：211；Package：TO-94；Two-Phase DC Fan Driver with FG

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SDC

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丝印：211AI01L；Package：SOIC；Low Skew, 1-to-2 Differential-to-HSTL Fanout Buffer

FEATURES • Two differential HSTL compatible outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any single-ended input signal to HSTL levels with r

文件：299.04 Kbytes 页数：15 Pages

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丝印：211AI01L；Package：SOIC；Low Skew, 1-to-2 Differential-to-HSTL Fanout Buffer

FEATURES • Two differential HSTL compatible outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any single-ended input signal to HSTL levels with r

文件：299.04 Kbytes 页数：15 Pages

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丝印：211BI03N；Package：SOIC；Low Skew, 1-to-2, Differential-to-LVHSTL Fanout Buffer

Features • Two differential LVHSTL compatible outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any single ended input signal to LVHSTL levels w

文件：489.14 Kbytes 页数：16 Pages

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丝印：211BI03N；Package：SOIC；Low Skew, 1-to-2, Differential-to-LVHSTL Fanout Buffer

Features • Two differential LVHSTL compatible outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any single ended input signal to LVHSTL levels w

文件：489.14 Kbytes 页数：16 Pages

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