Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

文件：94.1 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

文件：94.1 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

文件：94.1 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

文件：94.1 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体