Low Power Triple D-Type Flip-Flop

General Description The 100331 contains three D-type, edge-triggered master/slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data en

文件：101.34 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体

Low Power Triple D-Type Flip-Flop

General Description The 100331 contains three D-type, edge-triggered master/slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data en

文件：101.34 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体

Low Power Triple D-Type Flip-Flop

General Description The 100331 contains three D-type, edge-triggered master/slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data en

文件：101.34 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体

Low Power Triple D-Type Flip-Flop

General Description The 100331 contains three D-type, edge-triggered master/slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data en

文件：101.34 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体