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ISPLSI2064VE-100LJ44中文资料PDF规格书
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ISPLSI2064VE-100LJ44规格书详情
Description
The ispLSI 2064VE is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100 IEEE 1149.1 Boundary Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.
Features
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100 Functional, JEDEC and Pinout Compatible with ispLSI 2064V Devices
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 280MHz* Maximum Operating Frequency
— tpd = 3.5ns* Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
产品属性
- 型号:
ISPLSI2064VE-100LJ44
- 功能描述:
CPLD - 复杂可编程逻辑器件
- RoHS:
否
- 制造商:
Lattice
- 存储类型:
EEPROM
- 大电池数量:
128
- 最大工作频率:
333 MHz
- 延迟时间:
2.7 ns
- 可编程输入/输出端数量:
64
- 工作电源电压:
3.3 V
- 最大工作温度:
+ 90 C
- 最小工作温度:
0 C
- 封装/箱体:
TQFP-100
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
LATTICE |
23+ |
NA |
25060 |
只做进口原装,终端工厂免费送样 |
询价 | ||
Lattice Semiconductor Corporat |
21+ |
44-LCC(J 形引线) |
130 |
100%进口原装!长期供应!绝对优势价格(诚信经营 |
询价 | ||
LATTICE |
23+ |
PLCC |
3220 |
原装正品公司现货价格优惠欢迎查询 |
询价 | ||
LATTICE/莱迪斯 |
13+ |
PLCC44 |
1790 |
全新原装,支持实单,假一罚十,德创芯微 |
询价 | ||
LATTE/莱迪斯 |
23+ |
NA/ |
3441 |
原装现货,当天可交货,原型号开票 |
询价 | ||
LATTICE/莱迪斯 |
2022 |
PLCC |
80000 |
原装现货,OEM渠道,欢迎咨询 |
询价 | ||
LATTICE/莱迪斯 |
21+ |
PLCC44 |
1709 |
询价 | |||
LATTICE |
PLCC44 |
9500 |
一级代理 原装正品假一罚十价格优势长期供货 |
询价 | |||
LATTICE |
22+ |
PLCC |
2250 |
100%全新原装公司现货供应!随时可发货 |
询价 | ||
LatticeSemiconductorCorp |
23+ |
44-PLCC(16.58x16.58) |
66800 |
原装正品现货 |
询价 |